32-nm processes would continue to use planar MOSFETs.

32-nm CMOS begins to take shape

By Ron Wilson, Executive Editor -- EDN, 7/20/2006

At the Semicon West conference in San Francisco in July, the dim outlines of 32-nm CMOS began to take shape. The process will look more familiar to design teams than many had predicted, but the process is still far from business as usual. Pacing the still-tentative discussion of 32-nm technology, Applied Materials proclaimed that 32-nm processes would continue to use planar MOSFETs. This claim represents a major change from conventional wisdom, which declares that the 32-nm process signifies the dawn of the 3-D, multigate transistor. FinFETs, trigate MOSFETs, and fully depleted SOI (silicon-on-insulator) devices were all aiming to hit the mainstream at this process node.

http://www.edn.com/article/CA6355048.html?ref=nbnp