這個應該用 Verilog 或者 VHDL design 個 RTL 就可以了。不用物理實現

來源: Siriuc 於 2025-01-17 20:31:01 [舊帖] [給我悄悄話] 本文已被閱讀：次

WENXUECITY.COM does not represent or guarantee the truthfulness, accuracy, or reliability of any of communications posted by other users.