See this..現在一個四個結的門電路大概要100NM乘100NM

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Density of logic transistors (solid line) has advanced on average by 2× per generation. Dotted line is estimated density from pitch scaling alone. SRAM transistor densities, derived from bit cell area, 4 assumes 6-transistors per cell. Transistor density data points were obtained by dividing reported total transistors by reported die area 12 per chip.